Badge hardware

The board carries an ESP32-S3-WROOM-1U-N4R8 module (U2): a dual-core Xtensa LX7 with Wi-Fi 802.11 b/g/n and Bluetooth 5 LE, 4 MB of flash and 8 MB of octal PSRAM.

This corrects an earlier version of this page. It named the bill of materials’ ESP32-S3-WROOM-1-N16R2 (LCSC C2913205) — 16 MB of flash, 2 MB of quad PSRAM — and recorded the disagreement with the firmware build files as unresolved. It is resolved: the silicon was read directly on 5 August 2026, and the build files were right. The BOM line item is wrong.

Don’t trust either document over the board. The module suffix is printed on the shield, and the chip will answer for itself:

pio pkg exec -p tool-esptoolpy -- esptool.py --chip esp32s3 flash_id

On this board that reports Features: WiFi, BLE, Embedded PSRAM 8MB (AP_3v3) and Detected flash size: 4MB. Those two lines settle it: 8 MB of PSRAM on an ESP32-S3 module is the octal part, while the 2 MB R2 variant is quad.

Because this is an octal-PSRAM part, GPIO35, GPIO36 and GPIO37 are reserved by the PSRAM interface and must not be used. The current pin map avoids all three. A quad-PSRAM R2 part would not reserve them — which is why building against the wrong module can move a pin map that previously worked.

PSRAM is nevertheless disabled in every build, and deliberately so. Nothing in the firmware allocates from it — internal RAM sits at about 20% of 320 KB and the largest buffer is 2 KB — while PSRAM draws current continuously on a 50 mAh cell whose rail the rest of the design works hard to protect. The flags are present but commented out in platformio.ini, with the reasoning beside them.

A 2.13-inch monochrome e-paper panel drives over 4-wire SPI. It connects through CN1, a 24-pin 0.5 mm bottom-contact FPC connector, so the panel itself is not on the bill of materials.

The panel used by the current firmware is a GDEY0213B74 — 250 × 122 pixels, SSD1680 controller, driven with the GxEPD2_213_BN class. Its BS1 pin must be tied to ground for 4-wire SPI.

E-paper holds its last image with no power applied. Redraw only when something changes: a full refresh is slow and visibly flashes, so treat it as an event, not a frame rate.

USB-C in, regulated 3.3 V out, with a battery in the middle:

USB-C (USB1)  ──►  MCP73831 (U5)  ──►  3.7V LiPo
                                          │
                                          ▼
                                   AP2112K-3.3 (U3)  ──►  3V3 rail
                                                            │
                                          ESP32-S3, e-paper, buzzer

• USB1 is a 16-pin Type-C receptacle. R1 and R2, both 5.1 kΩ, are the CC pull-downs that make a USB-C source deliver 5 V.
• U5, an MCP73831T-2DCI/OT, is a single-cell linear LiPo charger. The 2 in the part code sets constant-current regulation; the programming resistor sets the actual charge current.
• U3, an AP2112K-3.3TRG1, is a 600 mA low-dropout regulator supplying the 3.3 V rail.
• R13 and R14, both 100 kΩ, form a battery-sense divider so firmware can read pack voltage on an ADC pin.

The board also carries a 47 µH inductor (L1), three MBR0530 Schottky diodes and an SI1308EDL MOSFET. That combination is consistent with a switching supply generating the e-paper’s bias rails, but the schematic was not supplied with the layout, so this page does not claim a topology it has not seen.

Every part is sourced from LCSC. Passives are omitted here; the designators below are the ones you would replace or probe.

U2 is the one row that does not match the bill of materials. The BOM specifies ESP32-S3-WROOM-1-N16R2 (LCSC C2913205); the module actually fitted is the N4R8 below, read from the silicon on 5 August 2026. Listed as fitted rather than as ordered, on the same principle as the rest of this page — the board wins.